1. Field of the Invention
The present invention relates to phase-locked loops (PLLs), and particularly to a digital phase comparator used in an entirely digital PLL.
2. Discussion of the Related Art
FIG. 1 is a schematic diagram of a conventional PLL structure. The PLL includes a voltage-controlled oscillator (VCO) 10 providing a frequency NF to a divide-by-N counter 12. A phase comparator 14 receives the output frequency F from divider 12 and a reference frequency Fref. The phase comparator 14 provides a phase error signal e to a filter 16 whose output c controls the VCO 10. In steady state, the phase and frequency of signal F are locked on signal Fref. In common applications, for example in the horizontal scanning of a television set, the frequency F to be obtained is approximately 15 kHz, and the frequency NF is approximately 12 MHz (N=768), and filter 16 is a low-pass filter whose cut-off frequency is a few hundred hertz.
The present trend is to realize all the PLL elements in the form of digital circuits. This avoids the use of high value capacitors that are difficult to integrate, renders the elements programmable, and simplifies the design operations by allowing the use of standard blocks in MOS or CMOS technologies.
FIG. 2 represents a conventional digital phase comparator 14. The phase comparator 14 includes a phase-frequency detector (PFD) 18 receiving the signals Fref and F. The PFD 18 provides pulses UP whose widths equal the phase lags of signal F with respect to the signal Fref, and pulses DOWN whose widths equal the phase leads of signal F with respect to signal Fref. An up/down counter 20 receives a clock signal CK having a high frequency relative to the frequency of signals Fref and F. The up-counting of the up/down counter 20 is enabled by pulses UP, and the down-counting is enabled by pulses DOWN. A sequencer 22 receiving signals F and CK resets the up/down counter 20 between two edges of signal F, once its content has been processed by the filter.
With this configuration, after each pulse UP or DOWN, the up/down counter 20 stores a digital value E corresponding to the desired phase error.
The two edges of each pulse UP or DOWN correspond to an edge of signal Fref and to an edge of signal F, respectively. Accordingly, if a spurious pulse occurs before the edge to be taken into account of signal Fref or F, the pulse UP or DOWN thus generated is erroneously shortened or lengthened. Such a phase comparator is not suitable to process TV horizontal scan signals because, in that case, the signal Fref may have many spurious pulses.
Moreover, to obtain a sufficiently accurate phase comparator, the clock signal CK must have a substantially high frequency. For example, for a TV horizontal scan, the frequency of signal CK must be approximately 200 MHz. Common technologies do not allow to realize such a fast up/down counter.